Operational Amplifier Design Project scope Design a differential input,…

Operational Amplifier Design

Project scope

Design a differential input, single-ended output operational amplifier which has a resistive

feedback network to achieve the desired closed loop gain.

The suggested resistor value between the output and inverting input is 10 The resistor

between the inverting input and ground sets the closed-loop gain.

The amplifier current bias reference is generated externally.

The amplifier has to meet the following performance criteria:

Table 1: Design parameters

Semiconductor process geometry 0.6µm

Minimum closed-loop gain 6dB

Dual power supply Vdd = +15V; Vss = -15V

Maximum quiescent power dissipation 50mW

External bias current 50µA

Minimum output current (source and sink) 5mA

Minimum Slew rate 15 V/µs

Input bias current

Minimum positive output voltage swing +13.5V

Maximum negative output voltage swing -13.5V

Maximum capacitance load 50pF

Minimum resistive load

Minimum open loop gain 100dB (100,000)

Minimum phase margin 45deg

Minimum gain margin 6dB

Minimum closed-loop bandwidth, (Cload = 5MHz

Figure 1: Example of circuit application.

Project design

The amplifier can be designed as an integrated circuit or as a discrete amplifier, your choice.

State the choice from the beginning of the project.

In an integrated circuit design the transistor, resistor and capacitor sizes can be modified. The

minimum dimensions are provided.

For a discrete application, the transistors have a fixed geometry and the only way to increase

size is to parallel them. Discrete components are off the shelf values that can be found in a

catalog or online resources such as Mouser or Digikey. Resistor values are off the standard 1%

list. To make nonstandard values, any component can be made of off the shelf values

connected in any combination of parallel and/or series.

Lists of standard 1% resistor values and capacitor values are provided in Appendix I and II and

can be also downloaded from the course site.

The amplifier has to use bipolar and MOS transistors. If you plan to use only one type of

transistor, please explain why. The transistor models are provided.

To build the amplifier, use a combination of circuits presented in the lecture. You have the

freedom to choose the circuit architecture, the number of gain stages, component sizing, etc.

The only requirement is to meet the specifications.

Remember: when it comes to circuit design, inspiration is good, copying is not.

A library with semiconductor transistor models is provided. The name of the library is

ECE5204_project_library.lib and can be downloaded from the course files.

transistor to open the parameter entry dialog. Change the transistor model at the top to

NMOS_5204 for NMOS device or PMOS_5204 for PMOS device. Continue to enter transistor W

and L in µm, such as, 1µ, see Figure 1. Optional, you can parallel transistors by using parameter

M.

If you plan to design a discrete amplifier,

the transistor name and pick a new one from the list.

Schematic entry

To place an NMOS or PMOS transistor use symbols

click over the

transistor to open the parameter entry dialog. Change

the transistor model at the top to NMOS_5204 for

NMOS device or PMOS_5204 for PMOS device.

Continue to enter transistor W and L in µm, such as, 1µ, see Figure 1. Optional, you can parallel transistors by

using parameter M.

If you plan to design a discrete amplifier, use symbols

name and pick a new one from the list.

To enter a bipolar transistor, place an NPN or PNP.

Then, hover over the model name, either NPN or PNP,

and right click. For NPN enter NPN_5204 and for PNP enter PNP_5204. If you choose a discrete approach, hover over the transistor until a hand pointing to the left is visible, right click and pick a new transistor from the list.

Figure 2: MOS transistor parameter dialog box

To parallel multiple bipolar and MOS transistors, a non-documented feature is available, arrays. The array syntax is Qx, where n is how many transistors are paralleled. For instance, if

transistor Q1 is made of 5 bipolar transistors in

parallel, right click on the reference designator Q1 and

change it to Q1.

The same technique works for MOS transistors too,

example M1.

There is a drawback to arrays, in the waveform viewer

each transistor in the area is shown separate not as a

sum of all transistors in the array.

Abridged transistor models for first approximation calculations

The following tables provide a minimum number of transistor parameters which can be used to

initially determine the circuit performance by first approximation.

For first approximation only basic parameters need to be calculated, such as transconductance,

output resistance.

The bipolar transit time helps to approximate the base-emitter capacitance, if needed. The

MOS parasitic capacitances are considered negligible, these will be taken into account by the

LTSpice simulator.

Table 2: MOS abridged parameters

MOS Transistors

Parameter NMOS_5204 PMOS_5204 Units

Threshold, Vto 0.7 -0.8 V

200E-06 65E-06 A/V2

Lambda, 1/VA 0.02 0.04 V

-1

Table 3: Bipolar abridged parameters.

Bipolar Transistors

Parameter NPN_5204 PNP_5204 Units

Current gain, 150 70

Saturation current, Is 2E-16 1.3E-16 A

Early voltage, VA 250 100 V

Base transit time, F 15E-09 25E-09 s

Project hints

The amplifier front end can be a differential amplifier. Usage of active loads is recommended

for integrated circuits. For discrete circuits the resistive loads can offer some advantages when

it comes to matching.

A good circuit design has the current and voltage offsets defined only by the input stage. This is achieved by maximizing the gain in the first amplifier stage. If needed, additional gain can be

achieved by one or more intermediate stages. Designing only one or two gain stages simplifies

the amplifier compensation for capacitive load stability. The output needs to biased and sized

according to the output current requirements.

The semiconductor process has a minimum geometry of 0.6µm. It is recommended to choose

the minimum MOS transistor gate length greater then 1µm.

First, approximate the gain of each stage without using computer simulation, approximative

calculations using lecture formulae and simplifications.

Use LTSpice to continue the design in order to meet the design requirements.

It is recommended (not mandatory) to use bipolar transistors for the output stage and build the current sources using MOS transistors. The front-end can be bipolar, MOS or a mix.

Project stages and requirements

Draft circuit

After the first week, present the following:

1) A draft circuit architecture.

2) Several calculated specifications, at the minimum, open loop gain, idle current and

bandwidth. These specifications do not have to be the final numbers, just your first

y

need to be in the ballpark, for instance within +/- 15% .

Final project submission

The project needs to be submitted by the end of the last course week with the following

documentation:

1) Complete electrical schematic.

2) a SPICE netlist which includes simulation benches

(.ac, .dc. .step statements)

3) Draw an equivalent small signal circuit of the entire amplifier.

4) First approximation calculations using formula from the lecture for the following

parameters: open-loop gain, open-loop bandwidth and common mode rejection.

5) Spice simulation plots indicating that the following parameters have been met:

1) Open loop gain

2) Closed loop bandwidth

3) Bode plots for 5 different capacitive loads up to the maximum specified capacitive

load showing phase and gain margin.

4) Output voltage swing across the minimum resistive load for a differential voltage

source freq = 1Hz (shows dc performance)

6) Table with performance specifications based on calculations and/or simulations.

Minimum closed-loop gain 6dB

Dual power supply

Quiescent power dissipation

Output current (source and sink)

Slew rate

Input bias current:

Positive output voltage swing

Negative output voltage swing

Maximum capacitance load:

Minimum resistive load:

Open loop gain

Phase margin

Gain margin

Closed-loop bandwidth, (Cload = 10pF,

:

Attachments: Project-Ampli….pdfFinal-project….docxECE5204-proje….libcapacitor-tab….pdfresistor-tabl….pdfApr 27 2022 02:20 PM

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